In the prior art, switches capacitor DAC circuits have relied on either a binary-weighted array of capacitors, a Capacitor 2-Capacitor (C-2C) ladder circuit, or a combination of both techniques to derive the output signal level. In such arrangements, N capacitor or ladder branches are switches so that the summation of charge from all branches is proportional to the desired analog output level. See, for example, Analog MOS Integrated Circuits, published by Wiley, at pp. 417 et.seq.
A primary disadvantage of these circuits is that the charge from each branch carries a sampled thermal noise component, proportional to kT/C, and an error component due to switch charge injection. Since, in these circuits, each branch's noise component is uncorrelated with the noise from the other branches, the individual noise variances in each branch are additive which results in a total noise variance of N*(kT/C). In order to maintain this noise at an acceptably small level, it will be appreciated that for many applications unacceptably large values of capacitance, C, can be required to obtain acceptable resolution. Also, the charge injected by each switch will sum and appear as an error voltage at the output.
Since power dissipation in these devices is also proportional to C, the resolution requirement must be met by also increasing the power requirement.